Principal Packaging Engineer

Principal Substrate and Packaging Engineer Fully onsite in the San Francisco Bay AreaFull time opportunity $400-500K total compensation package- base, bonus, stock (depends on skillset/experience level) Industry leader in semiconductor design focused on advanced IC packaging and high-speed interconnect technologies. In the role, you will have primarily be responsible for the layout, routing, and functionality of packages and substrates, including design of high-speed lines.What You'll DoDesign and layout advanced IC packages, substrates, and interposers, including high-speed signal routingCollaborate closely with electrical, mechanical, SI/PI, and program teams during front-end and detailed layoutDefine layout rules, panelization strategies, and stack-ups with substrate and package vendorsPerform peer design reviews and contribute to layout best practices and flow improvementsExecute DRC and LVS checks to ensure layout correctnessSupport post-fab evaluation, including visual inspection, electrical validation, and high-speed characterizationDevelop and apply script-based layout automation to improve efficiency and qualitySimulate layouts and recommend design optimizations to meet performance and reliability targetsRequired BackgroundBS/MS/PhD in Electrical, Computer, Mechanical Engineering, or related field10+ years of hands-on experience in IC substrate and package layoutDeep expertise with EDA layout tools, such as: Calibre/Klayout, Cadence Allegro Package Designer, Innovus and VirtuosoMultilayer and high-speed layoutRF design fundamentalsPackage/substrate manufacturing processes and materialsSurface-mount technology (SMT)

Created: 2026-05-08