Senior Validation Engineering Manager DDR

Senior Validation Engineering Manager DDR4/DDR5A leading chip and silicon IP provider is seeking an experienced Validation Manager to join its Memory Interface Chip business unit. In this role, you'll collaborate with some of the industry's top engineers and innovators to develop products that make data faster, more efficient, and more secure.This is a hands-on technical management role and requires approximately 20-30% day-to-day technical work alongside leadership responsibilities.Key Focus Areas & Technical ExpertiseBench validation and electrical characterization of high-performance memory buffer chipsDDR4/DDR5 memory characterization and validationStrong Python coding skills - must be capable of developing automation scripts and lab toolsExperience with SerDes or PCIe/PCIe PHY high-speed interfacesSolid understanding of signal integrity, power integrity, and high-speed I/O characterizationResponsibilitiesLead and directly contribute to hands-on bench validation and electrical characterization activities (20-30% of time)Manage and mentor a small team of 2-5 validation engineers, ensuring technical excellence and project alignmentPartner with Design, Architecture, Verification, and Operations teams to deliver top-quality buffer chip productsDevelop and continuously refine validation methodologies, improving design coverage, efficiency, and time-to-marketCollaborate with internal and external partners for test equipment sourcing, PCB fabrication, and assemblyDevelop automation frameworks and Python-based validation scripts for data collection and analysisDefine and execute test methodologies to validate silicon designs against specificationsContribute to project planning, budgeting, and resource allocationQualificationsB.S. or M.S. in Electrical Engineering or related field5+ years of hands-on bench validation experience in semiconductor or system-level environmentsProven experience with DDR4/DDR5 memory interfaces and processor/memory system architecturesDemonstrated proficiency in Python scripting for validation, automation, and data analysisBackground in SerDes or PCIe PHY characterization is highly desiredStrong understanding of electrical characterization, signal integrity, and power integrityExperience managing small teams or leading technical projects as an individual contributor with leadership responsibilitiesExperience with ATE or system-level testing is a plusExcellent communication, organizational, and cross-functional collaboration skillsLocation: San Jose, CA (Relocation assistance available)Duration: FulltimeSalary Range: $136,000 to $252,600 (DOE)Compensation: Medical, Vision and Dental Plan. Bonus: 20% RSUs: $145K total, vesting over 4 years.Submit resume to Jobs@No 3rd party agencies or C2CAbel Lara | 408.550.2800 x119Abel@

Created: 2026-05-08