Lead Test Engineer

Lead ASIC DFT EngineerWe are seeking a highly skilled Lead ASIC DFT Engineer to drive the architecture, implementation, and validation of Design-for-Test (DFT) solutions for complex ASIC and SoC designs. This role requires strong technical ownership across the full DFT lifecycle, along with hands-on expertise in silicon debug and test optimization.Key ResponsibilitiesLead DFT architecture, implementation, and sign-off for ASIC/SoC programsDefine and implement scan architecture, including scan insertion, stitching, and compressionDrive ATPG flowspattern generation, simulation, DRC checks, and coverage closureOwn MBIST/LBIST integration, verification, and debugPerform silicon bring-up, debug, and failure analysis for test-related issuesDevelop and validate DFT constraints (SDC) and support timing closureCollaborate with RTL, verification, physical design, and STA teams for seamless integrationSupport JTAG, boundary scan, and IP-level DFT integrationReview design flows to ensure high test coverage and qualityMentor engineers and contribute to DFT methodology improvements and automationRequired QualificationsStrong experience in ASIC DFT with end-to-end ownershipSolid understanding of DFT fundamentals, fault models, and test coverageHands-on expertise in:Scan architecture and ATPGMBIST/LBISTJTAG and boundary scanSilicon debug and bring-upExperience with Synopsys, Cadence, or Siemens/Mentor toolsFamiliarity with RTL design, synthesis, STA, and physical design flowsExperience with large SoC designs and hierarchical DFT methodologiesStrong problem-solving and communication skillsPreferred QualificationsExperience in post-silicon validation and debugKnowledge of iJTAG, SSN, and advanced DFT techniquesExperience with DFT SDC and timing closureScripting skills in TCL, PERL, or PythonExposure to yield analysis and manufacturing test optimization

Created: 2026-05-09