MEMS Design Engineer

Memory Interface Design EngineerBackgroundOur client is seeking an experienced Design Engineer with a strong memory-interface background to support fast-moving development efforts on high-speed memory subsystems. This team is looking for someone who has worked directly on memory controllers, PHYs, or related interface logic and can contribute in a hands-on environment with minimal ramp-up.ProjectThe engineer will support the design and implementation of memory-interface logic tied to DDR, LPDDR, HBM, or related architectures. The work will likely involve controller and/or PHY development, interface integration, timing and latency considerations, and close collaboration with adjacent design and verification teams. There is also interest in candidates with some coding or scripting experience to support debug, modeling, automation, or development efficiency.Required Skills5+ years of digital design engineering experienceStrong background with memory interfaces such as DDR, LPDDR, HBM, GDDR, or similarExperience with memory controller and/or PHY designStrong RTL design skills in Verilog and/or SystemVerilogExperience integrating high-speed interface logic into complex SoC or subsystem environmentsFamiliarity with timing, CDC, resets, training/calibration flows, and interface-level debugSome coding or scripting experience in Python, Perl, Tcl, shell, or C/C++Ability to work effectively in a fast-paced development environmentNice to HaveExperience with advanced packaging, memory product engineering, or HBM-related implementationsExposure to memory-chip behavior, signal integrity, or package-related reliability concernsExperience with bring-up, lab debug, or silicon validation tied to memory subsystems

Created: 2026-05-09