DFT ENGINEER

Scan insertion and ATPG tools (Synopsys, Cadence, Mentor).MBIST/OCC validation flows.Hierarchical DFT and SDC constraint management.Solid understanding of SSN design and JTAG standards for embedded instrumentation.Good understanding of SpyGlass DFT rules for design quality and testability compliance.Strong fundamentals in Digital Circuit Design and Logic Design.Good understanding of RTL design, synthesis, STA, and physical design flows.Hands-on experience with scripting (TCL, Perl, Python, Shell, etc.) for automation and flow development.Hands-on experience with silicon bring-up and debug.Good problem-solving, communication, and cross-functional collaboration skills.

Created: 2026-05-10