Staff Physical Design Engineer (Top-Level EMIR Signoff)

We are seeking a highly experienced Senior/Staff Physical Design Engineer specializing in Top-Level EMIR and Power Integrity Signoff for advanced-node SoC designs (5nm / 3nm / 2nm).The ideal candidate will have proven expertise in full-chip Static & Dynamic IR Drop analysis, Electromigration verification, PDN optimization, and power integrity closure across multiple successful tapeouts.You will work closely with RTL, Physical Design, STA, Packaging, and Foundry teams to drive power signoff readiness for high-performance silicon programs.Key ResponsibilitiesDrive top-level EMIR signoff for complex SoC designs.Perform full-chip Static & Dynamic IR Drop analysis.Execute Electromigration (EM) verification and closure.Optimize Power Delivery Network (PDN) for reliability and noise margins.Analyze voltage droop and high-frequency switching behavior.Debug power integrity issues and drive closure independently.Collaborate with STA and Physical Design teams to improve PPA and signoff convergence.Develop scalable methodologies to improve runtime and signoff quality.Present power integrity risks, status, and mitigation plans to leadership teams.Required Technical SkillsEMIR / Power IntegrityStatic IR DropDynamic IR DropElectromigration (EM)Voltage Droop AnalysisPower Integrity SignoffCurrent Density AnalysisPDN OptimizationToolsAnsys RedHawk-SCCadence VoltusEquivalent EMIR toolsAdvanced Node Experience5nm3nm2nmAdditional SkillsTcl / Python / Perl scriptingUnderstanding of OCV / AOCV / POCVStatistical timing methodologiesFull-chip signoff methodologiesPreferred QualificationsExperience with 2.5D / 3D IC packaging signoffFamiliarity with TSMC / Samsung / Intel signoff flowsExperience in HPC, AI Accelerator, or large-scale SoC programsStrong debugging and analytical skills

Created: 2026-05-10