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Principal Verification Engineer

Fidelis Companies - San Mateo, CA

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Job Description

Principal Verification Engineer Full Time OpportunityFully onsite in San Francisco Bay Area$450K+ Total Compensation- Bonus, Base, and RSU's (Depends on skillset and experience level)Industry leader and well-established semiconductor design organization building next-generation ASICs and custom AI accelerators. This team is responsible for delivering high-performance IP used across advanced compute and connectivity products.This role focuses on IP- and subsystem-level verification, including complex blocks such as SerDes and processor-based subsystems, within large SoC environments.What You'll DoOwn verification of IP blocks and subsystems used in advanced ASIC and custom AI chip designsArchitect and implement modern verification environments and reusable test benchesDefine and execute block- and subsystem-level verification strategies and test plansDrive verification closure using functional coverage, assertions, formal methods, and debugCollaborate closely with design, architecture, physical design, and validation teamsParticipate in bring-up and debug of complex IP, including high-speed and processor-based subsystemsRequired BackgroundBS/MS in Electrical Engineering, Computer Engineering, or equivalent experience10+ years of hands-on SoC / ASIC verification experienceProven experience architecting scalable verification environmentsDeep knowledge of industry-standard verification methodologies and toolsStrong expertise in:SystemVerilog & UVMRTL design and verificationBlock- and subsystem-level verification planningHands-on experience with:CDC checksFormal verificationFunctional coverageGate-level debugEmulation / acceleration toolsStrong debugging and problem-solving skills, with a track record of delivering under tight schedulesNice to HaveFamiliarity with SerDes architectures, protocols, and bring-upKnowledge of processor microarchitectures and bus protocolsExperience building and maintaining automated verification frameworksBackground working on large, complex SoCs with multiple IP integrations

Created: 2026-05-13

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