Mixed-Signal Digital Designer

MediaTek CPU team is seeking motivated professionals interested in RTL development for mixed-signal design to join our team as a Senior Digital Design Engineer.In this role, you will collaborate closely with both the architecture modeling team and the analog design team to:1. Develop digital designs using SystemVerilog RTL based on system architecture specifications.2. Collaborate with the design verification team to compile functionality verification plans.3. Provide design integration guidelines and work with upper-level integrators to resolve related integration issues.4. Conduct front-end design quality signoff checks5. Develop design verification testing specifications for the post-Si software team.You will gain the opportunity to develop state-of-the-art power and performance management used in High-Performance Compute (HPC) products, including the design of clock delivery networks (CDN) and power delivery networks (PDN) for modern CPU/GPU/NPU.Work Location: Austin, TX, or San Diego, CAJob ResponsibilitiesUnderstand Mixed-Signal IP Functionality: Comprehend the mixed-signal functionality and requirements through design specifications provided by the architecture owner.Interface Protocol Identification: Work with upper-level design integrators to identify sub-module interface protocols.Digital Design Development: Create quality digital designs using SystemVerilog RTL that meet the computational functions or control sequences specified in the design specifications and perform module-level verification using the provided SW-based verification environment.RTL Sign-Off Checks: Conduct RTL sign-off checks, including LINT, CDC, CLP, and SDC verification.Physical Design Collaboration: Supply necessary collateral for physical design, including SDC/UPF, and collaborate with the physical design team to perform performance-critical path analysis of the assigned design block.Design Functionality Validation: Work with the design verification team to ensure the designs functionality.RequirementsEducational Background: Bachelors or Masters degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.Industrial Experience: 4+ years of working experience in RTL design or mixed-signal system development.Digital Design Knowledge: Working knowledge of digital circuit design including but not limited to FSM, register file, memory system, bus handshake protocol, and algorithmic logic unit.RTL Coding Skill: Proficiency in SystemVerilog coding is required, along with working knowledge of design synthesis, power, performance, and area trade-offs.Communication and Teamwork: Strong communication, presentation, and teamwork skills.EDA Tool Proficiency: Familiarity with industry-standard EDA tools for RTL design simulation and quality check flows.Scripting Languages: Knowledge of scripting languages such as Tcl, Perl, and Python is a plus

Created: 2025-05-31