Principal Verification Engineer (Founding Team)

OverviewAs a Senior Hardware Validation Engineer, working hands-on at the frontier of silicon, AI, and ML-driven chip design. Collaborate with top engineers and innovators, pushing boundaries in world-class IP and SoC validation for next-generation devices. This range is provided by Brahma Consulting Group. Your actual pay will be based on your skills and experience "” talk with your recruiter to learn more.Base pay range$200,000.00/yr - $250,000.00/yrWhat You'll DoPartner directly with the Head of Hardware to validate complex silicon IP and SoCs (RISC-V, PCIe/CXL, NoC, standard I/O) based on dynamic client dependently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and reusable collateral.Build simulation and emulation-ready datasets and infrastructure; set up and run platforms such as Zebu and Palladium for rapid prototyping and proof-of-concept.Collaborate with architects, design leads, and AI/ML experts to generate robust validation coverage and tegrate company products into customer RTL, validation, and architectural pipelines seamlessly.Track emerging trends and advances in semiconductor and AI design automation.Develop internal benchmarks and datasets to evaluate and improve system performance from RTL to architecture.QualificationsBachelor's, Master's, or PhD in Electrical/Computer Engineering or related discipline.8+ years in semiconductor, EDA, or silicon design; 10+ years preferred.Multiple taped-out silicon cycles at leading companies (Apple, NVIDIA, Intel, AMD, Google, Broadcom, Synopsys, Cadence, etc.).Deep expertise in IP/SoC validation, emulation, and architectural/system-level verification. End-to-end silicon delivery experience is valued.Strong skills in SystemVerilog/UVM, C/C++, and scripting (Python, Bash) for automation and test environments.Hands-on experience with simulation and emulation (Zebu, Palladium) tools, Formal verification, microarchitectural checkers, and FPGA prototyping.Proven problem-solving, communication, and collaboration skills; ability to work independently and cross-functionally.Willingness to work in-person, 4+ days/week in Palo Alto.PreferredExperience with AI-for-chip-design or ML-driven design workflows.Verification of CPU/IO, NoC, PCIe, CXL, memory controllers, LPDDR, PHY, or related subsystems.Exposure to RISC-V and startups building from 0 to 1.Seniority levelMid-Senior levelEmployment typeFull-timeIndustrySemiconductor Manufacturing #J-18808-Ljbffr

Created: 2025-10-01