Principal Verification Engineer

Overview A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, you'll work alongside world-class engineers to develop advanced technologies that make data faster and more secure. As a key technical leader in the organization, the Principal Verification Engineer will be responsible for defining and executing verification strategies across multiple product lines and global sites. The ideal candidate will bring deep technical expertise, ownership mentality, and strong collaboration skills to help ensure robust, production-ready silicon. Responsibilities Technical leader for full-chip and block-level verification Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers Implement testbenches, monitors, and scoreboards using UVM methodology Achieve functional and code coverage goals to ensure quality and completeness Support silicon bring-up, lab testing, and debug in partnership with the System team Contribute to the development of verification flows, tools, and methodology Mentor and guide junior engineers within the team Requirements Proficient in System Verilog or Verilog with significant UVM methodology experience Significant Experience with standard ASIC Verification flow/software tools Simulation tools: Synopsys VCS, Cadence Xcelium Coverage & Analysis: Cadence IMC (Incisive Metrics Center) Experience with scripting in Linux/Unix environments Verification of DDR memory interfaces is desirable Experience working in Analog/Mixed-Signal Products is desirable Verification Methodologies: SVA (System/Verilog Assertions) is desirable Regression Management: Jenkins (CI/CD Integration) is desirable Demonstrated ability to lead and drive complex technical solutions A strong commitment & ability to work in cross functional and globally dispersed teams MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience Location: San Jose, CA; Agoura Hills, CA; Morrisville, NC; Johns Creek, GA (Hybrid) Type: Full-time Salary Range: $170,000-$196,000 (DOE) No 3rd party agencies or C2C Seniority level Mid-Senior level Employment type Contract Industries Appliances, Electrical, and Electronics Manufacturing Referrals increase your chances of interviewing at OSI Engineering by 2x Get notified about new Validation Engineer jobs in San Jose, CA . Fremont, CA $80,000.00-$100,000.00 1 week ago Sunnyvale, CA $111,000.00-$164,000.00 4 days ago Mountain View, CA $40.00-$60.00 1 month ago Sunnyvale, CA $111,000.00-$164,000.00 3 weeks ago Sunnyvale, CA $170,000.00-$240,000.00 5 days ago Sunnyvale, CA $139,000.00-$200,000.00 1 week ago Santa Clara, CA $140,000.00-$190,000.00 1 month ago San Jose, CA $90,000.00-$140,000.00 2 weeks ago Hardware Engineer, Platforms, University Graduate Sunnyvale, CA $105,000.00-$151,000.00 2 weeks ago Menlo Park, CA $139,000.00-$200,000.00 2 weeks ago Electrical Engineer, Abuse & Test Engineering San Francisco Bay Area $120,000.00-$150,000.00 3 weeks ago Mountain View, CA $130,000.00-$160,000.00 2 months ago Electrical Hardware Engineer (Early Career) Mountain View, CA $148,000.00-$172,000.00 7 hours ago Mountain View, CA $150,000.00-$230,000.00 2 months ago Newark, CA $110,000.00-$130,000.00 1 week ago Redwood City, CA $95,000.00-$155,000.00 2 days ago San Francisco Bay Area $100,000.00-$150,000.00 3 weeks ago Milpitas, CA $150,000.00-$180,000.00 2 weeks ago Redwood City, CA $95,000.00-$155,000.00 2 days ago Sunnyvale, CA $80,500.00-$131,813.00 2 weeks ago Sr VLSI Design Engineer (Physical Design, New College Grad, Masters) Electrical Engineer/Senior Electrical Engineer - Power Distribution Livermore, CA $75,000.00-$164,000.00 1 week ago Electrical Engineer/Senior Electrical Engineer - Electronic Systems Livermore, CA $75,000.00-$164,000.00 1 week ago Mountain View, CA $110,750.00-$130,295.00 1 week ago San Francisco Bay Area $120,000.00-$150,000.00 1 month ago Electrical Engineering Internship, Prototyping #J-18808-Ljbffr

Created: 2025-10-01