Sr. FPGA Digital Engineer

Do you want to work on JPL''s Spaceflight Projects? Apply now!This Jobot Job is hosted by: Juan CorreaAre you a fit? Easy Apply now by clicking the ''Apply Now'' button and sending us your resume.Salary: $150,000 - $220,000 per yearA bit about us:Mainly supporting JPL''s programs our projects range from supporting engineering, operations, manufacturing, and fabrication of major International Space Station segments to creating designs for small robotic components. Our small company atmosphere adds to our ability to provide cost-effective solutions based on our lean management structure, sound corporate infrastructure, and steady financial growth.Why join us? Competitive Base Salary! Extremely Competitive Equity Package! Flexible Work Schedules! Accelerated Career Growth!Job DetailsJob Description:Work with Design/Test/SW Engineers in verification and validation of System/Processor/FPGAsDevelop verification plan based on design specification and requirementsPlan and schedule assigned projects for timely completionDevelop verification environment using scalable, maintainable, and re-usableDevelop test plans, test benches and tests/sequences, creating sequencers, drivers, checkers, monitors, and predictors/scoreboards in a UVMApply formal methods to supplement simulation-basedSystematically analyze, track and resolve design bugs and improvement requiredDevelop maintainable and robust regression system.Required Skills:Bachelor of Science in Electrical Eng., Electronics Eng., Physics or Equivalent Field for Education requirements15 Years of ExperienceMust be a US citizenMust be able to pass a national agency checkMust be able to pass a pre-employment drug screeningStrong experience with verification methodologies such as UVM/OVM. UVM is preferred.Ability to develop test plans of complex systems containing multiple FPGAs and protocols.Strong experience in developing sequences using constraints random methodologyExperience with building a complete test bench infrastructure that support the test plan.Experience with bug/action item tracking and source control tools.Proficiency in both VHDL and System Verilog/VerlogExperience with coverage driven methodology using cover groups, cover directives, assertions of System VerilogAbility to analyze and debug RTL design issuesOther Desired Skills:Experience with formal and physical analysis tools (i.e, CDC/Autocheck/propcheck/Covercheck)Source control and bug tracking system knowledge (Git, Jira, etc)Scripting languages (Perl, Python, bash scripts)Experience with continuous integration (Jenkins or Bamboo)Interested in hearing more? Easy Apply now by clicking the ''Apply Now'' button.

Created: 2021-11-29