Senior Design Verification Engineer

Senior Design Verification Engineering Needed / Semiconductor / SoCThis Jobot Job is hosted by: Kevin SzilagyiAre you a fit? Easy Apply now by clicking the ''Apply Now'' button and sending us your resume.A bit about us:Come join a rapidly growing ultralow-power wireless semiconductor startup with headquarters located in San Diego, CA. If you are a Senior Design Verification Engineer this opportunity is for you! We are developing complete wireless solutions with significantly differentiated power dissipation/performance tradeoffs. Our innovative technology also dramatically improves wireless product flexibility and ease-of-use for product developers. We are looking for driven candidates to join our fast-paced and motivated team. This role is an excellent opportunity for someone that enjoys a small and agile group where you can make a great impact.Apply now to be considered!Why join us?Great working environment with excellent base salary and benefits.Job DetailsAs a Senior Verification Design Engineer, you will contribute towards our execution and design verification plans of 5G cellular base stations. You will work closely with our verification team in the US, India and Sweden.Key Responsibilities:Construct IP, SoC level test benches using verification components developed at the IP level. Test bench architecture for random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs.Develop and execute verification plans based on design specifications and collaboration with architects and designers.Construct HW/SW Co-VerificationJob RequirementsMaster''s degree in engineering (or equivalent).Five years of experience in design verification - Proven experience in full chip verification from test plan development to tape-out sign-off.Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.Experience executing block or chip-level verification plans.Experience with HW/SW Co-Verification - Developing test benches, test cases/use-cases, APIs, their execution, and debug.Excellent debug skills, with experience debugging RTL in block and/or chip-level environments.Extensive experience with a variety of verification tools and environments, and a deep understanding of their differences and capabilities to optimize the right methodology with schedules as the top priority.Experienced in SystemVerilog, UVM, and scripting languages like Python and terested in hearing more? Easy Apply now by clicking the ''Apply Now'' button.

Created: 2021-11-29