Physical Layout Design Engineer with Security Clearance

KBR is a global government services organization delivering full life cycle professional and technical services from over 60 U.S. and 40 international locations. Our core capabilities include logistics, engineering, science, cyber, intelligence and security services. WHAT TO EXPECT When you become part of the KBR team, your career opportunities are endless. We offer challenging assignments on some of the world''s largest and most complex projects where our customers have come to value us, because they know, We Deliver! Responsibilities include: * Create custom layouts of CMOS/BICMOS integrated circuit (IC) designs of analog, RF and mixed-signal circuits.* Provide chip floor planning and chip level integration of various analog, mixed-signal, and RF blocks in various silicon and III-V process technologies.* Perform layout design checks, such as DRC, ERC, ESD, pattern density & antenna.* Perform layout verification of designs (LVS).* Participate in chip tape-out job functions. Desired Qualifications: * Associate''s degree in a STEM related field with 4+ year of related experience. Or bachelor''s degree in a STEM related field with 2+ years of related experience.* Excellent verbal, written and interpersonal communication skills.* Understanding of LINUX commands and environment.* US Citizenship.* Current Secret/TS SCI clearance or able to obtain and maintain DoD security clearance per business requirements.* Deep understanding of microelectronic fabrication process and semiconductor electrical principals.* Knowledgeable of analog and RF layout techniques.* Experienced in using Cadence''s Virtuoso schematic & layout tools, Cadence PVS, and Mentor''s Calibre DRC/LVS verification tools.* Knowledgeable of using process design kits'' (PDK) design rule files, verification files, technology files and pcells.* Experienced working with

Created: 2025-10-04