Verification Engineer Position @ Santa Clara CA (Fully ...

Hi We have an urgent job opening with our Direct client. Job Title: Verification Engineer Primary Skills: ASIC/UVM , IP or SOC level verification Location: Santa Clara CA, Duration : 6+ Months (Fully Remote) Job Description: 100% remote work opportunity Education: Bachelor''s Degree required? Yes Verification Engineer for Memory Controller Significant UVM, SystemVerilog experience in complex test-benches Experience working with DRAM controller, PHYs, memory models is preferred Significant experience with general verification flows and metrics Excellent debug skills Working with big teams across multiple geographies EXPERIENCE AND EDUCATION: 7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong Verilog/SystemVerilog knowledge Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences Some experience with SVA or formal are preferred. Ability to debug design/TB failures using logfiles and waveforms Knowledge of scripting language (PYTHON or PERL) Strong analytical skills and attention to detail; Strong written and communication skills IF Interested please send Resume to sadeq(at)infobahnsw(dot)com - provided by Dice

Created: 2025-11-15