Silicon Design Verification Engineer

Location: Hybrid – Santa Clara, CA or Austin, TXType: Full-Time | Salary: $150K–$250K + Competitive EquityVisa Sponsorship: H-1B, O-1, OPT Available About the OpportunityInitio Capital is hiring a Design Verification Engineer on behalf of one of the most ambitious chip startups in the U.S.—a stealth-mode team redefining the future of AI and analytics acceleration.Backed by top-tier investors and built around a seasoned team from Apple, Intel, and Nvidia, this company is designing RISC-V–based silicon with tightly integrated AI acceleration and custom workloads in mind. This is an opportunity to work on deeply complex verification challenges that impact compute performance, efficiency, and reliability at the foundational layer of modern infrastructure. About the RoleAs a Silicon Verification Engineer, you'll take ownership of top-level verification for the company’s AI/analytics accelerator. You'll define and implement verification strategies, write test plans, build emulation-friendly testbenches, and partner with software and silicon teams to enable end-to-end validation. This role offers the chance to shape product and verification flow in a high-autonomy environment. What You’ll DoDevelop verification strategy and own DV execution for complex accelerator subsystemsWrite and maintain testbenches in SystemVerilog, C++, and PythonCreate coverage-driven and directed/random tests for full-chip and subsystem validationCollaborate with software, firmware, and architecture teams for co-simulationBuild infrastructure for emulation, simulation, and hardware bring-upDeliver high-quality silicon verification aligned with aggressive execution timelines What We’re Looking For5+ years of hands-on design verification (DV) experienceMS or PhD in Electrical Engineering, Computer Engineering, or related fieldStrong SystemVerilog, C++, and/or Python development skillsDeep understanding of computer architecture, SoC design, and memory/cache subsystemsProven experience verifying CPUs, GPUs, or custom acceleratorsFamiliarity with industry-standard DV methodologies (UVM, formal, coverage-driven, etc.)Experience enabling HW/SW co-simulation or working on firmware test coveragePast contributions to hardware/software co-design workflowsPrevious experience at early-stage silicon or systems startupsPassion for AI/ML workloads, compute acceleration, or chip performance optimizationEquity: Meaningful early-stage grantHybrid in Santa Clara, CA or Austin, TXCollaborate with industry leaders from the most respected names in semiconductorsWork on a moonshot AI-silicon vision with deep technical impact and upsideThis is the rare chance to define the performance boundaries of next-generation AI chips from the ground up.Apply now to be considered for this high-impact role. #J-18808-Ljbffr

Created: 2025-09-17