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Software Engineer, Physical Verification

Cadence Design Systems - San Jose, CA

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Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.This R&D engineer role is part of the global placement group of Cadence’s Innovus Place & Route product. This key Innovus R&D group is responsible for optimizing global placement, which decides the rough locations of the standard cells (basic circuit elements of a design). The global placement of an IC design is a critical step for various optimization objectives of a chip design, including timing (how fast a chip functions), power (the power consumption of the chip), and routing congestion (wiring of the circuits in the design with least detouring and no shorts).The Innovus product is a key product used by a variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, and AI. The work done in this high-performance team has a huge impact on the chip industry and products that are used in our daily lives.We are looking for talented candidates with a strong background in electronic design automation (placement background is a plus) and excellent software engineering skills, experience with multithreaded and distributed optimization. We are looking for individuals that can make the next breakthrough in the technology that we provide to our customers, making a big impact on the industry.Minimum Qualifications:Highly technical engineer with excellent problem-solving skillsC/C++ software development experience in a Linux environmentStrong understanding and extensive usage of data structures and algorithmsGreat communication skills and a strong desire to work with customersMS (Ph.D. track a plus) in Electrical Engineering or Computer SciencePreferred Qualifications:Knowledge of physical synthesis algorithms; global placement is a strong plusKnowledge of analytical solver, linear, non-linear, and combinatorial optimizationExperience in GPU programming and multithreadingPrior R&D experience working on IC physical design toolsHands-on experience using the above physical design tools for design closure and knowledge of physical design flows a plusExperience with Tcl and other scripting languagesThe annual salary range for California is $110,600 to $205,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr

Created: 2025-09-17

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