Lead Timing Methodology Engineer

This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Overview WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. The Role AMD is seeking an ASIC Design Engineer with experience scripting around the EDA tool environments to contribute to the development of an automated digital hardware implementation framework for large SOC designs. The candidate will maintain and enhance an established push-button automation flow which performs implementation of RTL through pre-netlist synthesis and static timing analysis. The candidate will also develop parsers to extract and waive key design metrics from industry-standard synthesis and timing reports. These metrics are published to a dashboarding system which the candidate will help improve to meet the needs of the RTL design teams. The Person High-energy candidates with strong written and verbal communication skills, and structured, well-organized work habits, will be successful. Team and goal orientation are essential. Key Responsibilities Maintain and enhance a fully automated RTL implementation flow environment facilitating pre-netlist synthesis, static timing analysis, and several other design flows Produce scripts to extract metrics from EDA tool shells for reporting purposes Recommend novel visualizations to incorporate into the reporting tools Analyze the automation’s architecture and skillfully integrate new features Support the automation of other flows such as TCM (timing constraints manager), LINT, DFT (Design for Testing), DRC (design rule checks), CDC (clock domain crossing), RDC (reset domain crossing), and CLP (Conformal Low Power checks) as well as a comprehensive regression solution that encompasses all the above Preferred Experience Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters Mix of EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts) Familiarity with synthesis and the full repertoire of frontend RTL implementation flows Proficient with scripting languages TCL, Perl, Python, CSH Proficient with Cron and LSF job control automation Strong analytical and problem-solving skills Academic Credentials Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering Location San Jose, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Seniority level: Mid-Senior level Employment type: Full-time Job function: Semiconductor Manufacturing Referrals increase your chances of interviewing at AMD by 2x #J-18808-Ljbffr

Created: 2025-09-17