SOC Verification Engineer

Join an ambitious, experienced team of silicon and distributed systems experts as a Design Verification Engineer. You will have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems and helps solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience in building comprehensive verification frameworks and executing simulation test plans for large-scale networking and computing chips. Ideal candidates are eager to grow in a fast-paced, dynamic startup environment. The default location is Mountain View, CA, but we are equally open to remote candidates. Roles & Responsibilities Perform end-to-end verification of a large SOC within the SOC DV team. Define and review comprehensive SOC verification plans, including test strategies, specific test cases, and coverage metrics. Cover various aspects of SOC verification, such as functional testing, integration verification, and performance verification. Key Qualifications Experience with large SOC verification. Familiarity with SystemVerilog/UVM. Minimum 3 years of experience in ASIC verification. Experience with block-to-SOC verification reuse methodology is a plus. Experience with firmware-based verification is a plus. Experience with large-scale SOC testbench performance optimization is a plus. Experience with high-speed interface protocols like PCIe, CXL, DDR, Ethernet is a plus. Experience with ARM SOC bring-up is a plus. Additional Details Seniority level: Mid-Senior level Employment type: Full-time Job function: Quality Assurance Industry: Internet Publishing Note: This job posting appears to be active, with recent notifications of similar roles and salary ranges in the area. #J-18808-Ljbffr

Created: 2025-09-17