Physical Design and Verification Engineer

Team Description:The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.Job Responsibilities and Description:The Physical Design and Verification Engineer will be responsible for leading the team efforts on the functional verification of neural recording and stimulation SoCs, which include low-power processors, digital signal processing, hardware accelerators, and analog/mixed-signal IPs. The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly.Required Qualifications:Bachelor of Science (B.S.) degree in computer science or a related field, or equivalent experienceMinimum 3 years of experience in digital ASIC verificationExcellence in SystemVerilogExperience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shellExperience with code coverage and regression setupPreferred Qualifications:Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard toolsExperience building test benches, testing, and debugging for a complex system-on-chipExperience in formal verificationFunctional modeling experience and logic verification with SystemVerilog, SystemC/C++Experience with IEEE-1801 (UPF) based design simulation flowsExperience with low power gate level simulationsExposure with low power formal verification flowsStrong hands-on experience in verification methodologies such as UVMKnowledge of ARM/RISC-V processor, AMBA busKnowledge of power aware verificationExperience with FPGA/emulationExperience with lab system bring up, writing diagnostic, and lab debuggingExperience with build tools such as CMake and Bazel #J-18808-Ljbffr

Created: 2025-09-17