Optoelectronics Packaging Design Engineer

OverviewWe are seeking a skilled and versatile Optoelectronics Packaging Design Engineer to lead the design and development of advanced IC packaging solutions for our cutting-edge laser and optoelectronic systems. In this role, you’ll work cross-functionally with hardware, manufacturing, systems, IC, and operations teams to drive packaging design from concept through production. You will own packaging development end-to-end—designing, simulating, prototyping, and qualifying IC packages and chip carriers that meet demanding performance and environmental requirements. This role is based at our San Francisco office and may involve some travel to interface with vendors and manufacturing partners.Location: Onsite in our San Francisco office, located in the Mission District. Must be within a 15-20-minute commute to Mission District to be considered for this role. Key Responsibilities Own the end-to-end development of high-performance IC packages and chip carriers—from design and simulation to qualification and production. Collaborate with cross-disciplinary engineering teams to develop rugged, high-reliability packages for advanced laser and optoelectronic ASICs. Partner with manufacturing and quality engineering to ensure smooth transitions from prototyping to volume production. Define and execute reliability and qualification test plans at both package and system levels. Lead failure analysis and root-cause investigations, driving continuous improvement. Support yield analysis and contribute to process improvements in silicon and microelectronic assembly. Manage vendor relationships: sourcing, DFM review, quoting, and procurement for components such as substrates, adhesives, coated optics, PCBAs, and custom tooling. Minimum Qualifications 5+ years of experience in semiconductor packaging or process development (or 2+ years with a relevant master’s degree). Proficient in 3D CAD tools (e.g., SolidWorks) and FEA simulation software (e.g., ANSYS). Hands-on experience with die bonding, wire bonding, and active optical alignment. Familiarity with packaging technologies including multi-layer ceramic, CMOS image sensors, BGA, and organic substrates. Experience in wafer-level processing (e.g., dielectric deposition, RIE, wafer bonding, lift-off, dicing, wafer testing). Working knowledge of failure analysis techniques: X-ray, SEM, cross-sectioning, 3D interferometry, DIC microscopy, destructive testing, etc. Preferred Qualifications Bachelor’s or Master’s degree in Materials Science, Electrical Engineering, Mechanical Engineering, or a related field. Experience with optical systems and/or automated test equipment (ATE) for package-level testing. Skilled in statistical process control and analysis for high-volume manufacturing. Experience in automated microelectronic/photonic assembly (e.g., wafer inspection, epoxy/solder die attach, vision inspection, underfill dispensing). Familiarity with automotive qualification standards such as AEC-Q100. #J-18808-Ljbffr

Created: 2025-09-17