Senior Design Verification Engineer (ASIC/RTL)

Account Delivery Manager at Infobahn Softworld IncPREFERRED EXPERIENCE:Experience with C/C++Experience with Verilog, System Verilog, and modern verification libraries like UVM10+ years of ASIC design verification experienceExperience / Background with DDR or Memory Controller. PHY Verification is a plusExperience with scripting languages like Python, Perl, and TCL is a plusCollaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verifiedUnderstanding of Design for Test methodologies and DFT verification experience is a plusProficient in debugging firmware and RTL code using simulation toolsKEY RESPONSIBILITIES:Develop and maintain tests for functional verificationBuild directed and random verification tests, debug test failures to determine root causes, and work with RTL and firmware engineers to resolve design defectsWork on functional and code coverage verificationProvide technical support to other teams #J-18808-Ljbffr

Created: 2025-09-17