Principal/Staff Design Engineer- Timing Expert

Job DescriptionPrincipal Engineer (Timing Expert): Perform independent integrated circuit level architecture definition, simulation, and verification for design using CMOS technology with little or no supervision.Principle Duties and Responsibilities:Work as a key member in a development team, perform IC level architecture on analog/digital circuit design and verification using deep submicron CMOS process technology. The individual needs to carry out assigned design independently and mentor/monitor the execution of the design team. Supervise layout work and collaborate with product engineering and test engineering for post-silicon verification and product characterization.Define circuit structure and product architecture, carry the design from front-end concept to back-end physical implementation, generate high-level product models, and provide occasional customer support.Responsible for analog and digital design architecture, knowledgeable on building blocks for ultra-low jitter PLL, PFD Link, digital filter, Fraction N divider, open-loop FOD with SSC, and higher performance output buffer.Collaborate with both analog and digital teams to define signals between analog and digital interfaces, circuit block performance, run top-level simulations, and ensure final product quality.Create and verify high-level system models in Matlab describing system design/architecture.Create and maintain documentation for related project work and improve design flow as needed.Knowledge, Skills, and Abilities:MSEE/PhD with a minimum of 5 years’ experience or BSEE with 7 years’ experience.Hands-on experience with Cadence tool set, Synopsys tool set, Spectre & Hspice simulation tools, Matlab, and layout tools.Ability to work as part of a team and collaborate across different groups.Mandarin language skills are a plus but not required. #J-18808-Ljbffr

Created: 2025-09-17