SOC Physical Design Verification Engineer - Full Time

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon PDV Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.ResponsibilitiesDevelop our PDV methodology and infrastructure to enable the verification flow of large SoCsPerform full chip integration and run the complete suite of physical verification checksProvide guidance to the implementation teams throughout the project to enable early convergence and final closureInterface with various internal and external design teams to ensure the high quality of their deliverables and successful integrationWork with the package and floorplan teams to define padring and bump map designCollaborate with our technology team to define flows and integrate foundry PDK dataRequirementsDeep understanding of the challenges associated with in deep sub-micron process nodesHands-on experience in closure and tapeout of large hierarchical designsExperience with industry standard physical verification tools (Siemens Calibre)Strong scripting skills in tcl and pythonAbility and taste for solving complex problems, efficient written and verbal communication, excellent organization skillsSelf starter and highly motivatedAbility to work cross-functionally with various teams and be productive under aggressive schedulesEducation and ExperiencePhD, Master’s Degree or Bachelor’s Degree in EE, EECS or CS. #J-18808-Ljbffr

Created: 2025-09-21