Signal and Power Integrity Engineer

Join the leading chiplet startup from the ground floor! As a Signal and Power Integrity Engineer, you will provide packaging solutions for chiplet interconnects in a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for design, modeling, manufacturing, assembly, and testing of traditional and advanced packaging for Eliyan’s chiplet solutions. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.Key ResponsibilitiesWorking closely with analog circuit designers to understand and define IO requirements co-designed with the channelResponsible for pre-layout and post layout channel simulation and optimization to achieve the best performanceUsing driver/receiver models to run transient channel simulation, inspect eye diagrams, and improve the performanceApplying best practices for the design of power delivery networks, extracting models, and performing DC/AC/transient simulationsUnderstanding substrate and interposer manufacturing design rules, assembly requirements, and driving the layout engineers to implement themPerforming measurements in the lab, correlating with simulation, identifying issues and providing solutionsQualificationsExpertise in signal integrity and power integrity simulation methodologiesExperience with simulation tools such as HFSS, Q3D, Siwave, PowerDC, PowerSI, ADS, Spectre, HSPICE, AllegroKnowledge of using lab equipment such as Vector Network Analyzer, Spectrum Analyzer, High-Frequency OscilloscopeBS degree in EE or equivalent, with 5 years of experienceWill not relocate for this role a this time and onsite requiredIdeal QualificationsPrevious experience of IC packaging, manufacturing, and advanced package designKnowledge of SERDES design, IBIS-AMI model creationMS degree in EE or equivalent, with 7 years of experience #J-18808-Ljbffr

Created: 2025-09-21