ASIC Engineer, Formal Verification

Summary:Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.Required Skills:ASIC Engineer, Formal Verification Responsibilities:Provide technical leadership in Formal VerificationPropose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block levelWork with Architecture and Design team to come up with formal specification and implementationDefine formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC levelBuild reusable/scalable environments for Formal Verification and deploying the toolsEvaluate and recommend EDA solutions for Formal VerificationProvide training for internal teams and mentoring engineers related to Formal Verification TechnologyMinimum Qualifications:Minimum Qualifications:Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of experience in Design Verification5+ years of experience in Formal VerificationExperience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etcProven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniquesProven analytical skills to craft novel solutions to tackle industry-level complex designsDemonstrated experience with effective collaboration with cross functional teamsFluency in hardware description languages, such as SystemVerilog and SVAProficiency in scripting languages such as Python, Perl, or TclExperience with JasperGold or VC-FormalPreferred Qualifications:Preferred Qualifications:Experience to quickly understand and interpret specifications and extract design behaviors/propertiesExperience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW acceleratorsExperience with complex SoCsFormal verification experience in clock domain crossing, IP-XACT based register verification and low powerExperience with development of fully automated flows from specification to fully verified designsExperience with simulators and waveform debugging toolsPublic Compensation:$173,000/year to $249,000/year + bonus + equity + benefitsIndustry: InternetEqual Opportunity:Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at . #J-18808-Ljbffr

Created: 2025-09-23