Sr. Principal Power Management Test Engineer

Sr. Principal Power Management Test EngineerExperience Level: ProfessionalJob Type: RegularLocation: San Jose, CA, US, 95134Requisition ID: 9277Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit to learn how our innovative team is helping connect, protect and power our planet. Responsibilities: Design PCB/probe card and socket according to R&D test plan and ATE test capability. Design and develop applications on various production test platforms for maximum throughput in a high-volume manufacturing environment. Experience in measurement methodologies for PMIC/PAC products: PMIC for mobile applications, Motor Control and Motor Drive, Battery Management and Fuel Gauge ICs. Participate in cross-functional teams to support engineering test projects, design verification testing, customer return case, qualification testing. Engage with Design Engineering to ensure products are properly designed for testability. Generate and maintain documents related to test systems, software designs and test development process. Perform correlation, Gage R&R, and ANOVA studies. Coordinate test program buyoff activities in lab & manufacturing sites. Qualifications: Bachelor of Science (BS) degree in Electrical, Electronic or Semiconductor Engineering or similar degree. 20+ years of relevant experience in developing Semiconductor devices as a Design, Test Development, or Application Engineer. Software development and debug experience on test systems. Familiar with ATE test platforms (preferably Cohu DMDX or Teradyne ETS-88). Understanding of power management devices with any of functional blocks: Buck, Boost, LDO, Charger, Driver, MCU etc. Experience with schematic design and PCB layout. Statistical engineering data analysis and DOE skill set. Strong working ownership with a very self-motivated and engineering attitude. Excellent written, oral, and interpersonal skills. This position is not eligible for visa sponsorship by the Company. Competitive base salary commensurate with experience: $191,200 - $248,600, relevant for the California Bay Area (subject to change dependent on physical location). Note: We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex, national origin, age, military or veteran status, genetic information, or disability. Nearest Major Market: San Jose #J-18808-Ljbffr

Created: 2025-09-25