Hardware Design and Test Engineer

OverviewJob Title: Senior Hardware Design and Test EngineerDuration: 12 Months contractLocation: San Jose, CAExperience: 10 to 15 years in hardware design and testingEducation: Bachelor s degree in Electrical Engineering, Electronics Engineering, or a related fieldRole OverviewWe are seeking a highly skilled Senior Hardware Design and Test Engineer to lead the development of embedded systems from concept to production. The ideal candidate will have extensive experience in hardware design, component selection, schematic creation, PCB layout review, and comprehensive hardware testing. You will play a critical role in all stages of embedded product development, ensuring high performance, reliability, and compliance with industry standards.Key ResponsibilitiesLead the design and testing of microcontroller and microprocessor-based hardware solutions, integrating peripherals such as ADCs, DACs, Ethernet PHYs, and storage devices.Select appropriate components balancing cost, performance, regulatory compliance, and longevity.Develop detailed schematics using Cadence OrCAD and provide PCB layout guidelines; review PCB layouts using Cadence Allegro.Design multi-layer PCBs with a strong focus on EMI/EMC mitigation and signal integrity.Execute board bring-up, functional validation, and design verification testing (DVT).Utilize hardware test equipment including oscilloscopes, logic analyzers, power supplies, and multimeters for debugging and validation.Collaborate closely across teams to ensure smooth progression through product development phases, including requirements analysis, design, prototyping, documentation, and testing.Required Skills & ExpertiseDeep knowledge of hardware interfaces including DDR3/4/5, PCIe Gen4 or newer, SATA, USB3.0/4.0, Ethernet, Display and Audio interfaces, SPI, and I2C.Proficiency with Cadence OrCAD for schematic capture and Cadence Allegro for PCB layout review.Strong troubleshooting and debugging capabilities with meticulous attention to detail.Excellent written and verbal communication skills.Preferred QualificationsExperience conducting EMI/EMC pre-compliance testing and coordinating with third-party test labs.Familiarity with reliability and robustness analysis techniques such as DFMEA, MTBF prediction, HALT, and ESS testing.Hands-on experience with cutting-edge high-speed interfaces (PCIe Gen5/6, USB4.x, DDR5, 10G/100G Ethernet).Expertise in signal integrity and compliance testing methodologies. #J-18808-Ljbffr

Created: 2025-09-29