Design Verification Engineer

Join to apply for the Design Verification Engineer role at Verilab Get AI-powered advice on this job and more exclusive features. Job Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel, present at conferences, win Best Paper awards, or get involved with industry standards. We do it all. In addition to being good, we like to be seen to be good. As a permanent full-time employee of Verilab, you will be responsible for all aspects of verification planning, management and implementation. You will be directly involved with helping build and grow client relationships. You will be working alongside some of the smartest people in the industry. Verilab is a company where your skills will be tested, nurtured, and where your contribution makes a difference. Requirements Key Qualifications BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science. 7 years of project-proven verification experience. Experienced SystemVerilog/UVM developer: Block and integration-level Coverage-driven, self-checking verification environments from scratch High-level sequence-based stimulus Complex transaction-based checkers (e.g., scoreboards with data translation and ordering) Register models Specification level checks for protocols like AXI, DDRx, PCIe, USBx. Verification planning: Requirements capture and traceability Estimation, prioritizing Metrics used to determine verification closure Ownership of work, from planning to implementation. Experience dealing directly with strict deadlines and technical challenges. Effective communication and collaboration with others. Other Interesting Qualifications Specman/e expertise or similar. C/C++ developing or integrating reference models into SystemVerilog/UVM environments. Formal Verification: Formal Property Verification, Proof Kits. Experience leading a technical team, including mentoring, training, and performing technical peer reviews. Embedded programming for ARM or GPU processors. Python or Perl. Benefits Full-time permanent employee with competitive salary. 20 days paid vacation and observed holidays. 401k Matching up to 6%. Medical, dental, vision, term life, AD&D, and disability (all premiums covered by Verilab). Eligibility for bonuses. Birthday gifts. Book budget. Leading industry career and personal development training. Additional Requirements All candidates must be eligible to work in the United States. Ability to travel is required. Seniority level Mid-Senior level Employment type Full-time Job function Engineering and Information Technology Industries Semiconductor Manufacturing #J-18808-Ljbffr

Created: 2025-10-08