A leading semiconductor company in Santa Clara is seeking a Senior ASIC RTL Design Engineer to develop cutting-edge designs for high-speed digital systems. You will collaborate with cross-functional teams to ensure successful product implementation while focusing on power management and RTL design optimization. Ideal candidates will have extensive experience with Verilog RTL development and a relevant degree. The role offers a full-time contract and competitive compensation, aligning with skills and experience. #J-18808-Ljbffr