Fpga Design Engineer

DescriptionWe are seeking a highly experienced Senior FPGA Design Engineer to lead the design, development, and verification of advanced, high‑performance FPGA solutions. This individual will play a critical role in defining system architecture and delivering robust, production‑ready designs for complex, high‑speed applications.The ideal candidate brings a minimum of 10 years of FPGA design experience, with deep technical expertise in high‑bandwidth interfaces such as PCIe Gen4/Gen5, 10–100G+ Ethernet, and DDR4/DDR5 memory systems. Strong proficiency in RTL design using VHDL, Verilog, and/or SystemVerilog is required, along with a demonstrated ability to achieve timing closure and address signal integrity challenges. Experience in cryptography, DSP, and RF‑based systems is highly desirable.This role requires ownership of FPGA development from initial concept through production release, including integration of vendor IP, optimization for low latency and high throughput, and comprehensive verification and lab validation. The Senior FPGA Design Engineer will work closely with cross‑functional hardware and software teams, provide technical leadership and mentorship, and ensure all designs meet stringent performance, reliability, and compliance standards.Key Responsibilities Lead the full FPGA development lifecycle, from requirements definition and architectural design through RTL implementation, verification, and system‑level integration across multiple FPGA platforms. Define, document, and review FPGA architectures, including block diagrams, clocking schemes, and design trade‑off analyses; actively participate in and lead design reviews. Develop high‑quality, reusable RTL and verification environments, including self‑checking testbenches, functional coverage models, and code coverage closure. Create and execute detailed verification test plans and procedures; generate comprehensive reports ensuring rigor, traceability, and compliance with project requirements. Collaborate with hardware and software engineering teams to support board‑level and system‑level integration, lab bring‑up, debugging, and qualification testing. Implement and validate JTAG boundary scan and other design‑for‑test (DFT) features; ensure adherence to testability, quality, and reliability standards. Drive continuous improvement in FPGA design methodologies, coding standards, and verification practices; mentor junior engineers and contribute to technical excellence across the organization. Skills & QualificationsMust:• Security clearance required.• BS or MS Degree in electrical/computer engineering at least 3-10 years of professional relevant experience• Familiarity using FPGA simulation and synthesis tools (e.g. Questasim, Synplify, Modelsim, Xilinx ISE and Vivado)• Strong oral and written communication skills and the ability to document and present work statusPreferred Additional Skills:• VHDL or Verilog• MATLAB modeling• Experience with hand coded implementations, above and beyond incorporating vendor COTS IP• Testbench development for the verification of RTL blocks• Experience verifying ASICs / FPGAs• Experience with building and setting up scalable simulation/verification environments• Experience with and understanding of Altera and/or Xilinx FPGA architectures• Good understanding of the Vivado and/or Quartus tool suite• Revision Control Systems: svn, git• Proficient in Linux Environments• Experience with high speed memory interfaces (DDRx)• Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions• Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust.• Experience with high speed serial protocols (PCI Express, SRIO, Ethernet)• Experience with Analog to Digital (AD) and Digital to Analog (DA) interfaces• Experience with control protocols such I2C, SPI, RS-232/422• FPGA lab validation with lab equipment (e.g Oscilloscopes, Logic Analyzers)• Experience with requirements management tool and change management tool (e.g. Jira)• Experience with Unix, scripting C, Python, bash/csh, etc• Experience with embedded System-On-Chip technologies, radio systems developmentJob Type & LocationThis is a Contract to Hire position based out of Melbourne, FL.Pay and BenefitsThe pay range for this position is $75.00 - $90.00/hr.Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)Workplace TypeThis is a fully onsite position in Melbourne,FL.Application DeadlineThis position is anticipated to close on Mar 5, 2026.About ActalentActalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email () for other accommodation options.

Created: 2026-03-04