Silicon Verification Engineer 3

Key Responsibilities include: "Looking for an experienced senior verification engineer with 15-20+ years of experience to participate in following activities: Understand complex architecture spec and write a new test-plan / review test-plans to provide feedback on missing test-cases UVM based TB development from scratch, including UVM sequence, scoreboard, coverage, assertions coding Implementing DPI Calls for C reference model for checking design functionality. UVM agent development including monitors, drivers etc. Able to work independently / solve problems without lot of handholding. Have prior experience in verifying SoCs and has knowledge of AMBA protocols. Experienced in block level and SoC level debug."

Created: 2026-03-04