Engineer, Senior|6288 Engineer, Senior|6288

Job Description: TOP 5 REQUIRED SKILLS: 1. 5+ years in Design Verification 2. 5+ years experience with SystemVerilog 3. 3+ years experience with UVM 4. 2+ years experience with ABH/AXI 5. 3+ years with System-on-Chip TECHNOLOGIES: SystemVerilog UVM Advanced Microcontroller Bus Architecture (AMBA) REQUIRED EDUCATION: Bachelor's Degree in Computer Science, Electrical/Electronics Engineering, Computer Engineering or related field and 5+ years of Hardware Engineering or related work experience -OR- Masters Degree in Computer Science, Electrical/Electronics Engineering, Computer Engineering or related field and 3+ years of Hardware Engineering or related work experience REQUIRED EDUCATION: 5 Years PHYSICAL REQUIREMENTS: NONE DRIVING REQUIREMENTS: NONE JOB DESCRIPTION: Principal Duties & Responsibilities: • Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. • Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. • Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs. • Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. • Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package. • Writes detailed technical documentation for EDA/IP/ASIC projects. •Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. • Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. • Develop Verification Methodology, ensuring scalability and portability across environments. • Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. • Develop Verification Plans and Testbenches for your functional domain. • Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. • Track and report DV progress using a variety of metrics, including Bugs and Coverage Comments for Suppliers: Qty of Submittals: 3 Comments for Suppliers: Onsite Critical 3 Interviews, Video 1 person on each interview 8:00 - 5:00 PM

Created: 2026-03-04