Senior RTL Design Engineer

Stealth Mode Start-Up - ASIC Design, RTL, ArchitectWe are seeking a Senior Design Engineer to lead architecture, design, integration, and implementation of advanced SoCs, with focus on high-speed interconnects, IP integration, and ASIC execution. Role emphasizes SoC integration with UCIe die-to-die interfaces, HBM subsystems, and custom compute cores.Responsibilities include RTL design, IP configuration and integration, synthesis, and collaboration with physical design teams for timing closure.Supports next-generation compute architectures, ensuring efficient interaction between UCIe, NoC interconnects, memory systems, and custom processing elements. Involves architecture definition and implementation of complex SoC and base die products.Key ResponsibilitiesDefine SoC and subsystem architecture (UCIe, NoC, memory controllers, PHYs, compute cores)Integrate high-speed IP (UCIe or similar) and configure NoC interconnectsDevelop micro-architecture, RTL, and perform RTL quality checksRun synthesis, lint, CDC/RDC, timing, power closure, and support silicon bring-upOptimize RTL for power, performance, and area; drive SoC performance simulationsCollaborate with physical design on floorplanning, CTS, routing, and power integrityRequired QualificationsBS/MS in Electrical or Computer Engineering (or related)10+ years ASIC/SoC design, integration, and implementation experienceTechnical ExpertiseSoC & RTL Integration: Verilog/SystemVerilog RTL design; top-level SoC integration of UCIe/HBM, memory controllers, and NoC interconnects; high-speed interface integrationASIC Implementation: Logic synthesis, STA, low-power design; EDA tool experience; physical design constraints, floorplanning, timing closure; formal verification (LEC)

Created: 2026-03-10