Senior Physical Design Application Engineer with ...

Job Details: Job Description: About Intel Foundry Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world class industry-leading IP portfolio that customers can choose from including , rich IP ecosystem including x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe. Position Overview We seek a Senior Applications and Solutions Engineer to provide technical support to Intel Foundry Services customers on PDKs, digital reference flows, and design signoff methodologies with specialized focus on Cadence tool suites. This role drives quality improvements in design kits through ASIC design reference flow validation and supports customers through successful tape-outs. Key Responsibilities Customer Technical Support & ImplementationProvide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologiesSupport and deliver ASIC/Digital tool/flow/ methodology solutions using Cadence tool suites to address customer issues and ensure successful tape-outsDrive customer success through expert guidance on advanced CMOS process implementation Quality Assurance & DocumentationDrive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation reviewCreate application notes, technical content, and deliver training presentations to customers and internal teamsEstablish and maintain quality assurance processes for design flow validation Design Flow Development & OptimizationDevelop and optimize digital design implementation flows for advanced CMOS processesSupport hierarchical and multi-voltage domain design approaches, timing and physical convergenceBuild and maintain quality assurance (QA) regression frameworks for design validation Core CompetenciesSelf-driven and results-oriented with ability to manage multiple tasks effectivelyStrong teamwork skills to drive solutions for customer design implementation challengesAnalytical problem-solving capabilities for complex design issuesExcellent communication skills with experience in collaboration and customer feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum QualificationsUS Citizenship requiredAbility to obtain a US Government Security ClearanceBachelor's degree in Electrical Engineering , Computer Engineering, Computer Science, or STEM-related field of study4 years of experience with advanced CMOS processes ( 22 n m and below)3 years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC)3 years of experience in one of the following scripting languages ( i.e. Python, Perl, Tcl , shell scripting) Preferred QualificationsActive US Government Security Clearance with a minimum of Secret levelPost Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of studyCustomer-facing experience in technical support rolesExperience with state-of-the-art process technology (7nm and below)Hands-on experience in Cadence EDA-based ASIC design implementation including full-chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verificationProficiency with Cadence EDA tools and flows: Innovus , Tempus, TempusECO , Pegasus, VoltusExperience with Synopsys tools (Fusion Compiler, PrimeTime , Prime ECO, ICV) is a plusExperience with hierarchical and multi-voltage domain design, top-down design, budgeting, and correlation across implementation and verification tools What We OfferOpportunity to work with cutting-edge digital design technologies for foundry servicesDirect customer engagement and technical leadership in advanced semiconductor designAccess to Intel's most advanced foundry technologies and comprehensive EDA tool suitesCompetitive compensationProfessional development in digital design methodologies and foundry servicesDirect impact on foundry customer success and advanced semiconductor innovation cj Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.Job posting details (such as work model, location or time type) are subject to change.ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.bfb3568a-762b-4989-884b-a9682aa104ca

Created: 2026-03-10