Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Mandatory skills and skill proficiencies required for this position: • Synopsys/Cadence EDA Verifications tools (Preference: 5) • SystemVerilog/UVM