FPGA Design/Verification Engineer

1 opening: 6 months: Active clearance: $100 MUST CURRENTLY HOLD ACTIVE SECURITY CLEARANCE. The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert. This engineer with have experience : -Verifying FPGA and/or ASIC designs including creating UVM verification environments, testbenches, tests and coverage. -Developing and finding more affordable ways to automate and develop verification scripts to improve FPGA verification efforts. Cross discipline collaboration with RTL Designers, Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. The selected candidate will also provide support and technical direction to junior engineers. Overall contribution to simulation, verification, integration & test of complex, high speed products. Preferred : onsite Sunnyvale, CA. Possible : onsite Denver CO. Will consider remote for the right candidate. MUST CURRENTLY HOLD ACTIVE SECURITY CLEARANCE.

Created: 2026-04-02