Sr. Digital Circuit Design Engineer

DescriptionKey Responsibilities:Design and implement sensor timing control logic and contribute to ISP system-level integrationParticipate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offsIntegrate and validate ISP data paths based on PRD, design specifications, and overall SoC architectureCollaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validationWork with physical design teams on floor planning, timing closure, and DFT implementationPerform full-chip integration and verificationSupport chip bring-up, validation, and silicon debuggingCollaborate with algorithm and application engineers on image tuning, optimization, and qualificationSupport silicon validation, debugging, and image quality tuning through production readinessQualifications:M.S. in Electrical Engineering or equivalent with 4+ years of relevant experienceStrong experience with ASIC design flow, including RTL design, simulation, synthesis, STA, formal verification, and DFTDeep understanding of end-to-end chip development: specification, architecture, low-power design, tape-out, silicon validation, debugging, mass production, and customer supportSolid knowledge of image sensor performance metrics, ISP architectures, and camera system integrationExperience with image sensors and camera systems is a strong plusAnnual base salary for this role in California, US is expected to be between $130,600 - $160,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role.EOE/Minorities/Females/Vet/Disability

Created: 2026-04-02