FPGA Engineer- Custom Compute Hardware

Ludwig Computing FPGA Engineer- Custom Compute Hardware Mill Valley, CA·Remote·Full time Company website Apply for FPGA Engineer- Custom Compute HardwareFPGA Engineer primarily focused on FPGA architecture, implementation, verification, and testing,About Ludwig ComputingHarnessing Randomness, Accelerating Compute;Creating the Foundational Technology for the Future of Intelligent ComputeDescriptionAbout us:At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance for various AI workloads. We are building a future where high performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.About the RoleWe are looking for a technically exceptional and intellectually curious Hardware FPGA Engineer who is passionate about hardware acceleration and wants to work on cutting-edge compute platforms. You will work directly with the founding team to assist in implementing and validating core logics, processing algorithms, and other subsystems. This is a hands"‘on, research"‘meets"‘build role in developing custom blocks for advanced computational workloads. This internship is primarily focused on FPGA architecture, implementation, verification, and testing, with opportunities to explore ASIC"‘relevant design flows and system"‘level integration in support of broader architectural development. Candidates interested in system"‘level digital prototyping and early"‘stage accelerator development are encouraged to apply. You must be comfortable working in a fast"‘paced team environment on a variety of R&D, proof of concept, and production programs.ResponsibilitiesTranslate architectural concepts into FPGA prototypesDesign and simulate custom processing modules using Verilog, VHDL, or high"‘level synthesis (HLS)Implement and validate processing components on FPGA platform using industry"‘standard tools (e.g., Vivado, Quartus, or OpenCL"‘based flows)Benchmark performance and optimize tradeoffs in latency, area, throughput, and memory bandwidthBuild testbenches, run timing/area analysis, and assist with system integrationWork collaboratively with system architects, FPGA design engineers, and embedded software engineersBe responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix.RequirementsExperience with FPGA development, RTL or HLS"‘based design in Verilog/SystemVerilog, VHDL, or C++Experience with FPGA development tools (Vivado, Quartus, or equivalent)Solid electronic circuit design and electronic systems backgroundExpertise of digital logic fundamentals, including pipelining and timing closureDigital system partitioning and advanced function implementation in FPGAs.Experience with memory mapping and hierarchy on FPGA.Strong skills in simulation, debugging, and synthesis workflowsB.S. degree or higher in engineering (preferably Electrical Engineering, Computer Science)Experience with OpenCL or HLS"‘based design targeting FPGAExperience with hardware/software co"‘design and system"‘level integrationProject experience in digital design, computer architecture, or embedded systems.Exposure to numerical computing, AI workloads, or custom arithmetic unitsExposure to ASIC design concepts, such as synthesis, floor planning, or RTL"‘to"‘GDS toolchainsFamiliarity with high"‘speed interfacesFamiliarity with analog or mixed"‘signal conceptsWhat You'll GainOpportunity to work on next generation AI compute architecturesHands"‘on experience building novel, high"‘speed, energy"‘efficient compute accelerators on FPGAsOpportunity to build skills that bridge into ASIC flows, including RTL quality, test benching, and synthesis"‘readinessExperience in connecting cutting"‘edge AI concepts to both low"‘level digital and potentially mixed"‘signal implementationsMentorship from a team with expertise in hardware"‘software co"‘design, digital architecture, and early"‘stage prototyping #J-18808-Ljbffr

Created: 2026-05-06