ASIC Intern - Digital/Mixed-Signal Design & Custom ...

Ludwig Computing ASIC Intern - Digital/Mixed-Signal Design & Custom Hardware Mill Valley, CA·Remote·Intern Company website Apply for ASIC Intern - Digital/Mixed-Signal Design & Custom HardwareInternship primarily focused on ASIC-level design, including RTL development, synthesis, and physical design readinessAbout Ludwig ComputingHarnessing Randomness, Accelerating Compute;Creating the Foundational Technology for the Future of Intelligent ComputeDescriptionAbout us:At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance for various AI workloads. We are building a future where high performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.About the RoleWe are looking for a technically exceptional and intellectually curious Hardware Design Engineer intern who is passionate about hardware acceleration and wants to work on cutting-edge compute platforms. You will work directly with the founding team to assist in implementing and validating core logics, processing algorithms, and other subsystems. This is a hands"‘on, research"‘meets"‘build role in developing custom blocks for advanced computational workloads. This internship is primarily focused on ASIC-level design, including RTL development, synthesis, and physical design readiness, with opportunities to explore FPGA-based prototyping and system"‘level integration as part of our broader hardware development process.ResponsibilitiesContribute to RTL"‘level design and microarchitecture development in Verilog or SystemVerilogPerform functional simulation, debugging, and testbench developmentSupport synthesis, static timing analysis, and LINTing/CDC checksCollaborate on design partitioning and integration with system"‘level blocksExplore PPA tradeoffs (power, performance, area) for candidate logic blocksWork with physical design constraints, floorplanning, and placement inputs when neededRequirementsStrong understanding of digital design fundamentals, including finite state machines, pipelining, and timing closureExperience writing RTL in Verilog or SystemVerilogFamiliarity with ASIC design tools and flows (e.g., Synopsys Design Compiler, Cadence Genus, or open"‘source equivalents)Understanding of synthesis and logic optimization conceptsAbility to work with waveform viewers, simulation tools, and debug workflowsCurrently pursuing a degree in engineering (preferably Electrical Engineering, Computer Science)Experience with OpenCL or HLS"‘based design targeting FPGAExposure to numerical computing, inference workloads, or custom arithmetic unitsFamiliarity with hardware/software co"‘design and system"‘level integrationPrior work with FPGA development boardsUnderstanding of memory system tradeoffsInterest in or exposure to ASIC design concepts, such as synthesis, floorplanning, or RTL"‘to"‘GDS toolchainsFamiliarity with analog or mixed"‘signal concepts where digital logic interacts with real"‘world signals (e.g., comparators, sense amplifiers, DACs)Currently PhD/MS student in EE/CSWhat You'll GainOpportunity to work on next generation AI compute architecturesFirst"‘hand experience building ASIC logic blocks that map to advanced compute conceptsOpportunity to explore digital and mixed"‘signal system design and how analog behavior can interface with structured digital logicThe opportunity to work on real logic that could be taped out, and understand what it means to go from RTL to GDSHands"‘on understanding of tradeoffs in high"‘speed, energy"‘efficient hardware designMentorship from a team with expertise hardware"‘software co"‘design #J-18808-Ljbffr

Created: 2026-05-06