Pre-Silicon Digital Verification Engineer

Role Number: 200631584-0836 Summary Join an accomplished team at Apple developing custom integrated circuits for Appleu2019s existing and future product lines. As a member of our PMU ASIC team, you will be responsible for verifying complex digital IPu2019s. You will work with the product teams, system architects, and digital designers, in refining microarchitecture specifications. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks. You will own the creation of the verification testbenches, using formal verification and UVM based simulation. Then you will build the testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.You will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal (and outstanding track record) of delivering bug free designs on the first tapeout. In addition to traditional digital circuit simulation, you will have the opportunity to learn and use other verification techniques such as formal verification, digital mixed signal verification, and analog mixed signal simulation using state-of-the-art tools. We have a flexible approach to problem solving that allows team members to tailor methodologies to optimize their productivity.Although the team is relatively small, we supply silicon to all of Appleu2019s industry leading hardware development teams, and work closely with the product teams and platform architects. We have a diverse, close-knit, high performing team ready to ready to welcome new team members of all experience levels. Join us in building Appleu2019s next generation products. Do you want to be a part of building the u201csurprise and delightu201d in Appleu2019s future? Description You will have the responsibilities as follows:Collaborate in developing precise design specifications for digital control blocksUse design specifications to create block and chip level verification plansArchitect and create block level verification elementsAssist in architecting chip and system level verification environments.Use System Verilog and UVM to develop drivers, tests, reference models and checkersDebug test failures and work with designers to develop fixesUse formal verification to prove assertions derived from microarchitecture specificationsUse functional and code coverage to track progress and gauge tapeout readiness Minimum Qualifications + BS and a minimum of 10 years of relevant industry experience Preferred Qualifications + At least 10 years of experience in ASIC pre silicon verification or design + Extensive course work in digital design and computer architecture + Foundation in object oriented programming techniques + Lab courses or work experience with System Verilog + Familiar with constrained random verification techniques + Familiarity with clock domain crossing design and verification techniques + Knowledge of digital ASIC development flow + Familiarity with power reduction techniques in digital ASICs Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (.

Created: 2025-11-15