Semiconductor Digital Architect

Architect next-generation digital subsystems and compute fabrics for 2.5D/3D microsystemsenabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.Define and optimize architecture specifications, dataflows, and interconnect topologies (chiplet fabrics, NoCs, HBM, PCIe/CXL) across heterogeneous dies.Collaborate with EDA, packaging, and system modeling teams to co-optimize digital architectures for performance, power, and reliability.Lead system-level modeling and design-space exploration for AI and signal-processing workloads using simulation and prototyping frameworks.Engage with industry partners and standards bodies (UALink, NVLink Fusion, UltraEthernet, CXL 3.x) to shape ecosystem directions.Mentor internal design teams on RTL methodologies, IP integration, and verification best practices for multi-die systems.Translate architectural innovations into roadmaps and reference designs, driving alignment between research, productization, and customer enablement.Other related functions as assigned.

Created: 2025-11-24