Sr Principal Silicon Engineer

Application close date:Applications will be accepted on an ongoing basis until the requisition is closed.At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflightThis role is part of Blue Origin corporate functions, providing centralized support across Blue Origin business unit teams, functions, and locations.At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflightThis is a foundational role in our Emerging Systems team. To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are bringing together technology from across our product lines to build the future of space-based communication.This role may be located onsite in Bay Area, CA. Candidates residing in or relocating to that location are approved for a temporary remote work exception while our local site is developed.Key Responsibilities:Lead the custom silicon technical strategy and architecture for a first-of-its-kind mission critical communications networkExecute complete partition synthesis and physical implementation workflows including synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checksDefine and execute a comprehensive verification and validation strategy with DFT and DFM feedback loopsCreate and enhance physical design methodologies and develop automation scripts to optimize implementation processesPartner with ASIC design teams to conduct architectural feasibility studies, establish timing/power/area targets, and evaluate RTL design tradeoffsCollaborate with cross-functional teams including systems, firmware, architecture, and product engineeringIdentify and resolve complex design challenges related to timing, congestion, and workflow bottlenecksPerform detailed debugging and closure of signoff issues in static timing analysis (STA), noise analysis, logic equivalency checking, physical verification, and power integritySupport lab integration and troubleshooting activitiesBasic Qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline10 plus years of hardware engineering experienceExperience with FPGA and/or ASIC designProficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)Experience with Linux development environmentExperience with design verification and test bench developmentPreferred Skills and Experience:Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related fieldExperience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPsKnowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM)Strong object-oriented programming and scripting skills (Python, TCL, Perl)Experience with physical design flows and industry-standard EDA toolsExperience with RTL2GDSII physical design and signoff flowsKnowledge of deep sub-micron FinFET and CMOS technologiesExperience with DFT/Scan/MBIST/LBIST methodologiesExperience mentoring junior engineersCompensation Range for:CA applicants is $177,857.00-$248,999.10;WA applicants is $177,857.00-$248,999.10

Created: 2025-12-15