Sr. RTL Design Engineer

General Summary:Role:u00a0As a Design Engineer, you'll play a critical role in shaping cutting-edge digital designs. Your responsibilities will include:- Micro-Architecture:u00a0Designingu00a0micro-architecture for both simple and complex digital, interface blocks.- RTLu00a0Development:u00a0Developingu00a0RTL (Register Transfer Level) code using industry best practices. This includes handling multi-clock designs, high-frequency requirements, low power, and low latency considerations while ensuring high performance.- Debugging and Post-Siliconu00a0Bring-Up:u00a0Troubleshootingu00a0andu00a0debugging issues during the development process and supporting post-silicon bring-up activities.- Documentation:u00a0Creatingu00a0comprehensive design documentation to ensure clarity and maintainability.- Designu00a0Optimization:u00a0Optimizingu00a0designs for key metrics such as area, power, and performance.- Cross-Functionalu00a0Collaboration:u00a0Collaboratingu00a0with cross-functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams.Must be in San Diego full time, 5 days a weekApplicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.u00a0 Must be a U.S. citizen and eligible to receive a U.S. Government security clearance Ideal candidate will have:- 5+ years of work experience with RTL/FPGA design (Verilog, System verilog), embedded system architecture and Verificationu00a0- Bachelor's degree in computer science,u00a0Electrical/Electronicsu00a0Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.- OR- Master's degree in computer science,u00a0Electrical/Electronicsu00a0Engineering, Engineering, or related field and 5+ year of Hardware Engineering or related work experience.- OR- PhD in Computer Science,u00a0Electrical/Electronicsu00a0Engineering, Engineering, or related field.Preferred Qualifications:- Positive Attitude:u00a0Bring a fun-loving attitude and a passion for inclusively solving problems.- Experience:u00a05+ years of ASIC design experience- RTL Expertise: System Verilog Design, Linting, CDC, Synthesis (FPGA and ASIC)u00a0- Testing: Building the test suites for design validationu00a0- Emulation: understanding of Emulation and prototyping flows for the design and validation in Lab is a big Plus.u00a0- Complex Digital Logicu00a0Design:u00a0Experienceu00a0with designing complex digital logic blocks and sub systems (CPU, GPU, DSP, Always on Systems, Digital interfaces (PCIe, UART, I2c, DDRx, SPI, USB).- ISAu00a0Familiarity:u00a0Knowledgeu00a0of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC-V.- Processor/Microcontrolleru00a0Systemu00a0Design:u00a0Understandingu00a0of processor or microcontroller system design.- Multi-Power Domain and Multi-Clock Domainu00a0Designs:u00a0Experienceu00a0with designs spanning multiple power domains and clock domains.- Scripting/Automationu00a0Languages:u00a0Proficiencyu00a0in scripting or automation languages like Python or Perl.- Industry Standard Digitalu00a0Tools:u00a0Familiarityu00a0with state-of-the-art industry-standard digital design tools.- Challenges of Lower Nodeu00a0Technologies:u00a0Awarenessu00a0of challenges faced when working with lower node technologies.If you're excited about pushing the boundaries of digital design and collaborating with diverse teams, we encourage you to applyMinimum Qualifications:u2022 Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring p ocess, rest assured that Qualcomm is committed to providing an accessible process. You may e-mailu00a0[](mailto:){rel=

Created: 2025-12-22