Senior Design Verification Engineer - QGOV

General Summary:Role:u00a0- Familiarity with RTL design in Verilog and System Verilogu00a0- Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.- Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc) .- Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals- Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches- Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.- Develop and maintain emulation environment to collect metrics related to emulation environment.Will need to be in San Diego full time, 5 days a weekApplicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.u00a0 Must be a U.S. citizen and eligible to receive a U.S. Government security clearance Required Qualifications:- 5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture- 5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flowsu00a0Relevant experience of 2-3+ yrs in any of the mentioned domain - Design/Verification/ ImplementationPreferred Qualifications:One or more of the following preferred:u00a0- Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.- Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology- Good understanding of chip-level functional model building- Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C- Knowledge of Behavioral and Structural models and familiarity with simulation environmentsu00a0u00a0- Experience customizing and debugging make-based build flows and working with Xilinx's Vivado tools- Experienceu00a0with cm tools such as Git and Gerrit.- Experience in formal / static verification methodologies will be a plus- Experience with emulation platforms -- Palladium, Zebu, Veloce, FPGAs.- Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.- Experience with C/C++ DPI transactors and monitors.- Develop and maintain emulation environment to collect metrics related to emulation environment.- Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.- Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.- Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.- Experienceu00a0with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.- Experience with GLS, and scripting languages such as Perl, Python is a plus- Linux OS proficiencyThe ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality.The candidate must be a team player and be flexible and open to a variety of task assignments within the team.Minimum Qualifications:u2022 Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mailu00a0[](mailto:){rel=

Created: 2026-01-26