Senior Analog Design Engineer

Adecco is hiring immediately for a Senior Analog Design Engineer with a local client in Santa Clara, CA. Pay is $120.00/hr - $150.00/hr. Duties: u00b7 We are looking for a hands-on senior-level engineer with good analog mixed-signal CMOS design background. u00b7 In this role, you will assist with the design of mixed-signal integrated circuits for innovative semiconductor fabrication tools. u00b7 If you have a strong ability to learn, good analysis & problem-solving skills, are enthusiastic about questioning current norms and pushing the boundaries of technology, this is the ideal position for you. u00b7 Our tight-knit group offers a unique opportunity to grow your design skills while you collaborate in the development of different types of analog mixed-signal circuits such as bandgap voltage reference, low-noise amplifiers, comparators, mixers, data converters, active filters, oscillators, etc. u00b7 Negotiate specifications with internal customers and other stakeholders. u00b7 Translate IC fabrication process capabilities into real world designs. u00b7 Design, simulate, and verify basic analog and digital CMOS circuits. u00b7 Review and supervise custom layout of analog circuits at the block & chip level. u00b7 Design experiments, test boards, and test programs for silicon characterization. u00b7 Assist with evaluation and troubleshooting of bench tests during silicon characterization. u00b7 Schedule tasks and goals to complete designs on time that meet all specifications. Qualifications: u00b7 M.S. in Electrical Engineering (or equivalent) with at least 5 years of industry experience in design of mixed-signal ASICs. u00b7 Analog circuit design experience in DACs, ADCs, current drivers, linear regulators, and other various supporting circuitry in CMOS processes. (high voltage experience is a plus). u00b7 Good understanding of IC device physics, spice models, ESD, latch-up, and manufacturing technology are also required. u00b7 Proficient in the use of Cadence's IC design environment (Virtuoso Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (System Verilog). u00b7 Knowledge of mixed mode simulation (Cadence AMS Designer) is a plus. u00b7 Previous experience with testing and characterization of ASICs is very desirable. u00b7 Proficiency in the use of Python to generate test code for silicon verification & characterization. u00b7 Knowledge of lab equipment including digital oscilloscopes, signal generators and Semiconductor Automatic Testers (Advantest/ATE). Click on apply now for immediate consideration for this Senior Analog Design Engineer in Santa Clara, CA. We look forward to hearing from you Benefit offerings include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and 401K plan. Our program provides employees the flexibility to choose the type of coverage that meets their individual needs. Available paid leave may include Paid Sick Leave, where required by law; any other paid leave required by Federal, State, or local law; and Holiday pay upon meeting eligibility criteria. Pay Details: $120.00 to $150.00 per hour Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable. Equal Opportunity Employer/Veterans/Disabled Military connected talent encouraged to apply To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable: + The California Fair Chance Act + Los Angeles City Fair Chance Ordinance + Los Angeles County Fair Chance Ordinance for Employers + San Francisco Fair Chance Ordinance Massachusetts Candidates Only: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Created: 2026-01-28