Senior Physical Design Engineer

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoftu2019s expanding Cloud Infrastructure and responsible for powering Microsoftu2019s u201cIntelligent Cloudu201d mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Microsoftu2019s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Physical Design Engineer to join the team. Responsibilities In this high impact role, you will be responsible on the following high level aspects: u2022 Responsible for Hierarchical Design Planning and partitioning strategies. u2022 Responsible for RTL to GDS implementation in Physical Design domain. u2022 Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential. u2022 Help influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. u2022 Execute floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA). u2022 Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. u2022 Develop guidelines, checklists, and best practices for top-level physical design. u2022 Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes. u2022 Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset. u2022 Demonstrate technical expertise across various domains of Physical Design & Timing Signoff. u2022 Clear communications on project status & planning. u2022 Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion. Qualifications Required Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Other Requirements: + Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter Preferred Qualifications: u2022 BS/MS in Electrical or Computer Engineering or any related degree u2022 Preferred 8+ years of experience in semiconductor design. u2022 Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. u2022 Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. u2022 Experience in hierarchical design work, Design Planning and integration with multiple production tape-outs using advanced foundry process nodes. u2022 Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. u2022 Own complete PD execution of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required. u2022 Proficient in integration activities and design planning (DP) methodology with hands-on experience. u2022 Good understanding of timing constraints (functional & DFT), static timing analysis (STA), and timing-power optimization. u2022 Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA). u2022 Hands-on experience with clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs. u2022 Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). u2022 Skilled in industry-standard EDA tools (Synopsys or Cadence). u2022 Mentor junior engineers on technical aspects. u2022 Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies. u2022 Demonstrated ownership of deliverables and strong cross-functional teamwork. u2022 Proven track record in mentoring, influencing teams, and driving alignment through clear and effective communication. u2022 Strong analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python. #SCHIE #CSME Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. (

Created: 2026-01-30