SoC UPF Methodology Engineer

Role Number: 200645465-0157 Summary Are you passionate about crafting solutions to intricate challenges? Join the Low Power groupat Silicon Technologies and contribute to the development of cutting-edge technology andcapabilities for low-power chip design. Your work will fuel Appleu2019s next-generation chipsYouu2019ll play a crucial role in exploring AI/ML to design the workflow for the next generation ofUPF. Additionally, youu2019ll refine our existing UPF framework and ensure its seamless integrationand rigorous verification across our mobile products.You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs. Description In this role, your main objective will be to enhance our Unified Power Format (UPF)methodologies, refining power intent specification, execution, and validation to support state-of-the-art mobile SOCs. Key responsibilities encompass:u2022 Enhancing power intent coverage via advanced static and dynamic verification techniques.u2022 Developing tailored UPF solutions to align with unique project requirements.u2022 Overseeing UPF deployment and sign-oufb00 for frontend (FE) and place-and-route (P&R) stages.u2022 Conducting thorough power intent assessments on custom circuitry.u2022 Partnering with design and verification teams to troubleshoot and fix UPF-related workflowchallenges.u2022 Integrating AI/ML technologies to optimize UPF processes and methodologies. Minimum Qualifications + A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience Preferred Qualifications + We are looking for a professional with deep knowledge in ASIC design methodologies, + emphasizing power management. Preferred skills include: + u2022 Expertise in UPF implementation and verification. + u2022 Proficiency in scripting with languages like Python and Tcl. + u2022 Understanding of CMOS power design principles. + u2022 Experience applying AI/ML to coding and workflow optimization. + u2022 Knowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP). + u2022 Familiarity with the complete RTL-to-GDSII design flow. + u2022 Strong communication abilities for eufb00ective collaboration across multidisciplinary teams. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (.

Created: 2026-02-13