TPU PCIe RTL Design Engineer

TPU PCIe RTL Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 5 years of experience in ASIC design, including one project focused on PCIe logic. + Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl. + Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. + Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM. + Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows. Preferred qualifications: + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. + 8 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic. + Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning. + Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up. + Experience in PCIe architecture, including Link Training and Status State Machine (LTSSM), TLP/FLIT pipelines, flow control, ordering rules, and performance tuning. + Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, youu2019ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Youu2019ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers. As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. Beyond designing high-performance PCIe subsystems, you will build the foundational SoC infrastructureu2014including clocking, reset, error handling, and chip managementu2014that powers our silicon. Your highly cross-functional role offers a

Created: 2026-03-07