Principal Mixed Signal Engineer, Texas Institute for ...

Design and develop high-speed mixed-signal I/O circuits for UCIe 2.5D and 3.0D die-to-die interfaces in 2.5D/3D microsystemsenabling robust, low-latency chiplet interconnect across AI, HPC, and defense platforms.Architect and optimize SerDes, clock/data recovery (CDR), equalization, and transceiver circuits for high-speed die-to-die and chip-to-chip links, including UCIe, PCIe physical layers.Collaborate with packaging, EDA, and system modeling teams to co-optimize mixed-signal I/O performance across heterogeneous integration stacksaccounting for signal integrity, power delivery, crosstalk, and thermal effects unique to 3DHI.Lead silicon bring-up, bench characterization, and production testing of high-speed I/O and mixed-signal circuitsdeveloping test methodologies, ATE programs, and yield-improvement strategies from prototype through volume production.Engage with industry partners and standards bodies (UCIe Consortium) to influence specification development and ensure TIEs physical-layer implementations remain standards-aligned.Mentor internal design teams on mixed-signal design methodologies, high-speed measurement techniques, and production test best practices for multi-die systems.Translate mixed-signal design innovations into IP roadmaps and reference designs, driving alignment between research, productization, and customer enablement for UCIe-based chiplet ecosystems.

Created: 2026-05-02